Apparatus and methods for a test and measurement instrument employing a multi-core host processor

ABSTRACT

The method for a test and measurement instrument includes the steps of: providing a test and measurement instrument; attaching a Device Under Test (DUT) to a signal source to be measured with at least one channel of the signal source in electronic communication with at least one of the acquisition modules; collecting data from the DUT; storing the collected data from the DUT in the acquisition module(s); dividing the collected data from the DUT into a plurality of pieces; assigning the plurality of pieces to the plurality of system buses; transferring the plurality of pieces to the memory connected to the processors by moving the plurality of pieces in parallel over their assigned system buses; processing the plurality of pieces with the plurality of processors; and displaying the results obtained by processing the priority of pieces with the plurality of processors.

CLAIM FOR PRIORITY

The subject application claims priority from U.S. Patent ApplicationSer. No. 60/913,525, entitled, APPARATUS AND METHODS FOR A TEST ANDMEASUREMENT INSTRUMENT EMPLOYING A MULTI-CORE HOST PROCESSOR (Sedeh, etal.), filed 23 Apr. 2007, and assigned to the same assignee as thesubject invention.

CROSS-REFERENCE TO RELATED CASES

The subject application is related to the following U.S. patentapplications, bearing attorney docket numbers 8361-US0, 8287-US1,8287-US2, and 8287-US4, all claiming priority from U.S. PatentApplication Ser. No. 60/913,525, entitled, APPARATUS AND METHODS FOR ATEST AND MEASUREMENT INSTRUMENT EMPLOYING A MULTI-CORE HOST PROCESSOR(Sedeh, et al.), filed 23 Apr. 2007, and all assigned to the sameassignee as the subject invention.

FIELD OF THE INVENTION

The present invention relates to an apparatus and method for a test andmeasurement instrument for use in connection with analyzing waveforms.The apparatus and method for a test and measurement instrument haveparticular utility in connection with providing a scalable test andmeasurement instrument capable of handling the acquisition, transfer,analysis, and display of large quantities of waveform data as well ascomplex waveforms.

BACKGROUND OF THE INVENTION

Apparatuses and methods for a test and measurement instrument aredesirable for providing a scalable test and measurement instrumentcapable of handling the acquisition, transfer, analysis, and display oflarge quantities of waveform data as well as complex waveforms. Demandfor new oscilloscope application features is growing, especially theability to process ever-greater quantities of waveform data, becausesignals are becoming increasingly complex. Analyzing complex waveformsgenerates more intermediate data, which in turn requires more systemmemory access instances.

Most software applications have enjoyed regular performance gains forseveral decades, even without significant modifications, merely becauseof increases in computer hardware performance. Central Processing Unit(CPU) manufacturers and, to a lesser degree, memory manufacturers havereliably increased processing speeds and lowered memory access times.However, performance gains through increasing CPU clock speeds areseriously inhibited by heat generation, electron leakage, and otherphysical limitations, while system memory speeds have historicallydoubled only every 10 years.

Since major processor manufacturers and architectures can no longereasily boost straight-line instruction throughput, performance gains intest and measurement instruments, such as oscilloscopes, will have to beaccomplished in fundamentally different ways. Because CPU manufacturershave adopted dual core and multicore processors to increase performance,oscilloscope applications will have to enable concurrent processing inorder to exploit the CPU performance gains that are becoming available.What is therefore needed is a practical apparatus and a realizablemethod that provides a scalable test and measurement instrument capableof handling large quantities of waveform data as well as complexwaveforms.

The use of oscilloscopes is known in the prior art. For example,oscilloscopes currently manufactured by Tektronix, Inc. of Beaverton,Oreg. ship with a single core 3.42 GHz Pentium® processor from Intel.These prior art oscilloscopes cannot have their performance boostedthrough use of a faster single CPU because CPUs with higher clock speedsdo not presently exist. Furthermore, mere replacement of the single coreCPU with a dual core or multicore CPU offers minimal benefit becausemany of the important operations of an oscilloscope application are notCPU constrained. In an instrument that moves and processes a largequantity of data, system memory access times and/or system busperformance often are the instrument's performance bottleneck.

Existing high-end oscilloscopes, such as those currently manufactured byTektronix, Inc., already incorporate a sizable system memory (2 GB ofsystem RAM is typical). Because of increasing quantities of data to beprocessed and stored, next-generation oscilloscope architectures willundoubtedly require additional memory. Since increases in main memoryspeeds are realized infrequently, the time required to access systemmemory is likely to continue to dominate many applications' performance.Therefore, the addition of a multicore processor to existingoscilloscope architectures provides minimal benefit because systemmemory cannot provide data as fast as the processors can process it.

Furthermore, the data acquisition process is an inherently sequentialfour-step process presenting additional challenges to the adoption ofmulticore CPU technology in oscilloscope applications. FIG. 1 depicts asingle core processor prior art oscilloscope architecture that acquiresand combines waveform data from four channels 120-126 into a single datarecord in the system memory 114. Conventionally, waveforms are stored inthe local memory 130 of the acquisition hardware 118 in a first step andsubsequently transferred serially to the system memory 114 via aPeripheral Component Interconnect (PCI) or Peripheral ComponentInterconnect Express (PCIe) system bus 116 and bridge 112 in a secondstep. The CPU 110 then analyzes the waveform data in a third step andcauses the results to be shown on a display screen 128 in a fourth andfinal step. The acquisition hardware 118 may be embodied in a peripheraldevice attached to the system bus 116 that is operable by the operatingsystem.

This four-step process is not easily amenable to parallelization. Thesefour subtasks cannot be run at the same time on four CPU cores with thisprior art architecture because each must be completed before the nextcan begin. Nor can these four subtasks be pipelined either. In thiscontext, a pipeline is a set of data processing elements connected inseries so that the output of one element is the input of the next one.The elements of a pipeline are often executed in parallel or in atime-sliced fashion. However, because three of the steps require accessto the system memory to run and store intermediate data generated asdata moves through the pipeline, parallel processing is impossible.Therefore, the inherently sequential nature of the data acquisitionprocess prevents taking full advantage of multicore processortechnology.

The system memory also creates a bottleneck because it is used forwaveform storage data and shared by several clients, including Analysis,General Purpose Interface Bus, Display, Acquisition, Math, Save/Recall,and Applications. Because these clients must access the data seriallyfrom the shared system memory, it is impossible to create parallelismamong the clients and run them at the same time. The architecture's datatransfer rate and system bandwidth also pose limiting factors, which arelikely to worsen. Next-generation real-time data acquisition hardwarewill have very large record lengths per channel. Existing oscilloscopearchitectures cannot transfer, analyze, and display that much data inreal-time.

An initial prior art attempt to address some of these problems was theTDS-7000-series oscilloscope manufactured by Tektronix, Inc. whosearchitecture is depicted in FIG. 2. This architecture employed a dualcore processor. Although each processor could access the other's memory,this was accomplished using the Direct Memory Access (DMA) process overa PCI bus, a relatively slow computer bus. An inability to transfer datasufficiently rapidly to continuously occupy both processors left theoscilloscope unable to take full advantage of the presence of twoprocessors.

FIG. 3 shows a prior art oscilloscope system architecture employing aquad core CPU 300 developed by the inventors of the current invention. Aquad core CPU 310, 328, 330, and 332 is the dominant high-performancecomputer architecture in industry, known as Symmetric Multiprocessor(SMP) architecture. While the SMP architecture performs adequately inmany respects, it unfortunately exhibits architectural limitations. Inan SMP-based system, all processors access a shared pool of memory 314over a central memory bus. While this limited the effectiveness of thedual core system depicted in FIG. 2, an even greater problem with memoryaccess occurs when quad core or higher multicore CPUs are utilized.Because the processors are often fighting each other for access to thesingle memory bus, a serious bottleneck develops. This occurs becausethe time to move data back and forth between the processors 310, 328,330, and 332 and the system memory 314 increases. This major bottleneckis especially severe in an instrument like a high-end oscilloscope.High-end oscilloscopes require the movement of large amounts of data andutilize processor-intensive applications that create considerabletraffic between the processors 310, 328, 330, and 332 and the systemmemory 314. Data sets in modern high-end oscilloscopes can be so largethat they are not entirely cacheable, resulting in many system memoryaccess instances. This problem with memory access times is aggravated byuse of the same system bus and memory bus for Input/Output (I/O) and DMAtransfer of waveform data from the acquisition hardware's 318 localmemory 334.

Another architectural problem with SMP architecture is that the memorysystem does not scale up with increasing numbers of processor cores.Memory access occurs via a single memory controller 522 (shown in FIG.5) for the entire system, no matter how many processor cores arepresent. This serious problem prevents taking full advantage ofmulticore CPUs because they cannot obtain enough data in a timelyfashion to always remain busy because memory is a shared resource. Thus,performance of applications with large memory requirements remainslargely constrained by memory access times.

Preliminary performance testing on dual core and quad core highperformance oscilloscopes using the architectures depicted in depictedin FIGS. 2 and 3 showed no significant performance gains over singlecore instruments. The lack of performance gains was not surprisingbecause the prior art data acquisition process is sequential in nature.All processor cores must share the system memory, and applications tendto be highly memory intensive. Because the memory system cannot providedata as fast as the application needs it to keep all of the processorcores busy simultaneously, very little parallel processing can occur,making the additional processor cores only marginally utilized.

Therefore, a need exists for a new and improved apparatus and method fora test and measurement instrument that can be used for providing ascalable test and measurement instrument capable of handling theacquisition, transfer, analysis, and display of large quantities ofwaveform data as well as complex waveforms. In this regard, the variousembodiments of the present invention substantially fulfill at least someof these needs. In this respect, the apparatus and method for a test andmeasurement instrument according to the present invention substantiallydeparts from the conventional concepts and designs of the prior art, andin doing so provides an apparatus primarily developed for the purpose ofproviding a scalable test and measurement instrument capable of handlingthe acquisition, transfer, analysis, and display of large quantities ofwaveform data as well as complex waveforms.

SUMMARY OF THE INVENTION

The present invention provides an improved apparatus and method for atest and measurement instrument, and overcomes the above-mentioneddisadvantages and drawbacks of the prior art. As such, the generalpurpose of the present invention, which will be described subsequentlyin greater detail, is to provide an improved apparatus and method for atest and measurement instrument that has all the advantages of the priorart mentioned above.

To attain this, the preferred embodiment of the present inventionessentially comprises the steps of: providing a test and measurementinstrument; attaching a Device Under Test (DUT) to a signal source to bemeasured with at least one channel of the signal source in electroniccommunication with at least one of the acquisition modules; collectingdata from the DUT; storing the collected data from the DUT in theacquisition module(s); dividing the collected data from the DUT into aplurality of pieces; assigning the plurality of pieces to the pluralityof system buses; transferring the plurality of pieces to the memoryconnected to the processors by moving the plurality of pieces inparallel over their assigned system buses; processing the plurality ofpieces with the plurality of processors; and displaying the resultsobtained by processing the priority of pieces with the plurality ofprocessors. The preferred embodiment of the present invention may alsocomprise multiple acquisition modules having signal bus interfaces witheach system bus being connected to its own acquisition module and havingits own acquisition hardware. Each piece of acquisition hardware is adirect memory access machine that can transfer data to any portion ofthe memory. There are, of course, additional features of the inventionthat will be described hereinafter and which will form the subjectmatter of the claims attached.

There has thus been outlined, rather broadly, the more importantfeatures of the invention in order that the detailed description thereofthat follows may be better understood and in order that the presentcontribution to the art may be better appreciated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram view of a prior art single CPU oscilloscopearchitecture;

FIG. 2 is a block diagram view of a prior art dual CPU oscilloscopearchitecture;

FIG. 3 is a block diagram view of a quad core CPU oscilloscopearchitecture;

FIG. 4 is a block diagram view of the current embodiment of theapparatus and method for a test and measurement instrument constructedin accordance with the principles of the present invention;

FIG. 5 is a block diagram view of a multicore processor suitable for usewith the present invention;

FIG. 6 is a block diagram view of the current embodiment of theapparatus and method for a test and measurement instrument of thepresent invention;

FIG. 7A is a block diagram view of the data flows in the prior artsingle CPU oscilloscope architecture;

FIG. 7B is a block diagram view of the data flows in an embodiment ofthe apparatus and method for a test and measurement instrument of thepresent invention;

FIG. 8 is a block diagram view of the current embodiment of theapparatus and method for a test and measurement instrument of thepresent invention;

FIG. 9 is a block diagram view of the current embodiment of theapparatus and method for a test and measurement instrument of thepresent invention depicting how data from a single channel can beassigned to multiple processor cores for parallel processing;

FIG. 10 is a block diagram view of the current embodiment of theapparatus and method for a test and measurement instrument of thepresent invention depicting how data from multiple channels can beassigned to multiple processor cores for parallel processing;

FIG. 11 is a flowchart view of a method of processing waveform data froma single channel of the present invention; and

FIG. 12 is a flowchart view of a method of processing waveform data frommultiple channels of the present invention.

The same reference numerals refer to the same parts throughout thevarious figures.

DESCRIPTION OF THE DRAWING

A preferred embodiment of the apparatus for a test and measurementinstrument of the present invention is shown and generally designated bythe reference numeral 10.

The principles of the present invention are applicable to a variety ofcomputer hardware and software configurations. The term “computerhardware” or “hardware,” as used herein, refers to any machine orapparatus that is capable of accepting, performing logic operations on,storing, or displaying data, and includes without limitation processorsand memory; the term “computer software” or “software,” refers to anyset of instructions operable to cause computer hardware to perform anoperation. A “computer,” as that term is used herein, includes withoutlimitation any useful combination of hardware and software, and a“computer program” or “program” includes without limitation any softwareoperable to cause computer hardware to accept, perform logic operationson, store, or display data. A computer program may, and often is,comprised of a plurality of smaller programming units, including withoutlimitation subroutines, modules, functions, methods, and procedures.Thus, the functions of the present invention may be distributed among aplurality of computers and computer programs. The invention is describedbest, though, as a single computer program that configures and enablesone or more general-purpose computers to implement the novel aspects ofthe invention.

FIGS. 4 and 6 illustrate improved apparatus for a test and measurementinstrument 10 of the present invention. More particularly, anarchitecture for the apparatus for a test and measurement instrument 10is depicted with every oscilloscope channel 22, 34, 46, and 58 coupledto its own single or multicore CPU 12, 24, 36, and 48, creatingacquisition pipes 60, 62, 64, and 66. For example, oscilloscope channel22 is connected to acquisition pipe 60 by acquisition module 20.Acquisition module 20 collects data from oscilloscope channel 22 via asignal source bus 68 and includes a demux ring 76 that separates thecollected data into separate files, each one containing at least oneelement of the original file. System bus 18 connects acquisition module20 to bridge 16. Bridge 16 integrates the data from the system bus tothe single or multicore CPU 12. Bridge 16 is connected to single ormulticore CPU 12, which is in turn connected to system memory 14. Systemmemory 14 stores incoming data from system bus 18 as well asintermediate and final calculations generated by a single or multicoreCPU 12. Each acquisition pipe has its own system bus 18, 30, 42, 54,system memory 14, 26, 38, 50, single or multicore CPU 12, 24, 36, and48, acquisition module 20, 32, 44, and 56 with local memory 84, 86, 88,and 90, signal source bus 68, 70, 72, and 74, and demux ring 76, 78, 80,and 82. Therefore, all of the acquisition pipes can operatesimultaneously and converge in the display subsystem 68, with eachbridge being directly connected to the display. This enables thecollected data to be observed much faster than is the case with priorart oscilloscope architectures. The oscilloscope's operating systempulls all of the individual system memories into one global addressspace, distributes threads across the CPUs, and maps a thread's memoryrequests to local system memory or remote system memory. Local systemmemory refers to the memory directly connected to a CPU, which can beaccessed the fastest. Remote system memory refers to the memory directlyconnected to the other CPUs. While it can be accessed by the first CPU,it takes longer. The global address space combines all of the individualsystem memories into a virtual single system memory accessible by theoperating system. Threads enable a program to split itself into multiplesimultaneously executing tasks. Multiple threads can be executed inparallel on many computer systems, such as those employed by the presentinvention.

In this architecture, the memory bottleneck of conventional SMParchitectures is removed because each channel has its own system memoryand CPU, so data remains in proximity to the CPU that needs it. However,as shown in FIG. 6, each CPU can access each of the other CPUs' memoryusing high-speed interconnects 76, enabling measurements thatincorporate data from multiple channels. The high-speed interconnects 76can be arranged in the square pattern shown, which enables eachprocessor to communicate with its two neighbors directly, butcommunication with the processors at opposite corners requires the useof one of the neighboring processors as an intermediary. Alternatively,there can be additional high-speed interconnects 76 connecting the CPUsin an X pattern in the middle to enable every CPU to have a directconnection to every other CPU, eliminating the need for using theneighboring CPUs as intermediaries when communicating with theprocessors at opposite corners. This design is presently more expensive,but it delivers improved performance. In addition, memory bandwidthscales linearly with the number of acquisition pipes. Compared to aconventional four-channel oscilloscope, a four-channel oscilloscope withthe improved architecture of the current invention increases the systemmemory bandwidth by a factor of four. All four acquisition pipes havetheir own memory 14, 26, 38, and 50, memory controllers 78, systemrequest interfaces 80, and crossbar switches 82, which enables all fouracquisition pipes to receive data in parallel.

This architecture also enables system I/O bandwidth to scale linearlywith the number of acquisition pipes. A four-channel oscilloscope withthis architecture has a system data transfer rate that is four timesthat of a conventional four-channel of oscilloscope because data can betransferred at the same time from all four channels using all fouracquisition pipes simultaneously. The oscilloscope's processingcapability also scales upward as the number of acquisition pipesincreases because the number of CPUs increases.

FIG. 5 illustrates the architecture of a prior art multicore processor500 suitable for use with the present invention. For example, the AMD64Opteron™ dual core processor, manufactured by AMD Corporation ofSunnyvale, Calif., has a Non-Uniform Memory Access (NUMA) architecture500 especially suitable for use with the present invention. The designis called non-uniform because memory access times vary depending uponthe memory's location. This is because a CPU can access its own localmemory 530 faster than it can access another CPU's memory. This designfeature gives processor cores 510 and 512 access to their own localmemory 530 via memory controller 522. When additional multicoreprocessors 500 are present with their own local memory, the high-speedinterconnects 524, 526, and 528 can be used to access their localmemory. This architecture enables each processor to access otherprocessors' memory quickly and easily. The high-speed interconnects 524,526, and 528 also enable communication with the data source channels,while the memory controller 522 also provides access to the system bus.The system request interface 518 and crossbar switch 520 control thephysical connections between the CPU cores 510 and 512, the memorycontroller 522, and the high-speed interconnects 524, 526, and 528.

FIGS. 7A and 7B illustrate the differences between data flows in theprior art oscilloscope architecture 100 and that of the presentinvention 10. More particularly, while data collected by the acquisitionhardware 118 can be processed only serially by a single CPU 110 in theprior art oscilloscope architecture 100, the present invention 10enables parallel processing of data from one channel by breaking it intoparts and supplying them to multiple CPUs 12-48 for analysis. Thequantity of CPUs assigned to process data from a single channel can bevaried in software from a single CPU to the maximum number of CPUsavailable in the oscilloscope. Applying more CPUs to process data from asingle channel greatly increases the data acquisition performance fromthat channel. Similarly, pipelining the display process between all ofthe available CPUs greatly increases display performance. Because eachCPU 12-48 has its own local memory 14, 26, 38, 50, such pipelining isfeasible and eliminates the need for hardware acceleration for displaypurposes.

FIG. 8 illustrates how the internal high-speed interconnects 68-74 of amulticore Non-Uniform Memory Access processor, such as the one depictedin FIG. 6, can be used as a faster system bus than the prior artdepicted in FIG. 2 that uses a PCI system bus 216. The high-speedinterconnects 68-74 enable much faster data transfer than does the PCIsystem bus 216, both because the high-speed interconnects 68-74 areinherently faster and because they are a dedicated data transferresource instead of being shared.

FIGS. 9 and 10 illustrate how waveform data from a single channel (FIG.9) and multiple channels (FIG. 10) can be broken into pieces andallocated by software to any combination of the available CPUs foranalysis. By dividing the data into multiple pieces, all of theacquisition pipe 60, 62, 64, and 66 can be used in parallel to acquire,transfer, analyze and display data. This approach generates results muchfaster than does the conventional serial process. These processes areillustrated in flowchart form in FIGS. 11 and 12, respectively.

The invention also includes a method of processing waveform data from asingle channel, which is depicted in FIG. 11. The method of processingwaveform data from a single channel consists of the following steps:obtaining the test and measurement instrument (810); attaching the testand measurement instrument to a device under test (820); acquiringwaveform data from the device under test using a single channel (830);dividing the waveform data into a plurality of pieces (840); assigningeach one of the plurality of pieces to a respective one of a pluralityof processors for processing (850); processing the plurality of pieceswith the plurality of processors (860); and displaying the resultsobtained by processing the plurality of pieces with a plurality ofprocessors (870).

The invention also includes a method of processing waveform data frommultiple channels, which is depicted in FIG. 12. The method ofprocessing waveform data from multiple channels consists of thefollowing steps: obtaining the test and measurement instrument (910);attaching the test and measurement instrument to a device under test(920); acquiring waveform data from the device under test using aplurality of channels (930); dividing the waveform data into a pluralityof pieces (940); assigning each one of the plurality of pieces to arespective one of a plurality of processors for processing (950);processing the plurality of pieces with the plurality of processors; anddisplaying the results obtained by processing the plurality of pieceswith the plurality of processors (960).

While current embodiments of the apparatus and method for a test andmeasurement instrument have been described in detail, it should beapparent that modifications and variations thereto are possible, all ofwhich fall within the true spirit and scope of the invention. Withrespect to the above description then, it is to be realized that theoptimum dimensional relationships for the parts of the invention, toinclude variations in size, materials, shape, form, function and mannerof operation, assembly and use, are deemed readily apparent and obviousto one skilled in the art, and all equivalent relationships to thoseillustrated in the drawings and described in the specification areintended to be encompassed by the present invention. For example, anysuitable specialized processor such as Graphics Processing Units (GPUs),Digital Signal Processors (DSPs), and Field Programmable Gate-arrays(FPGAs) may be used instead of the general-purpose single or multicoreCPUs described. And although providing a scalable test and measurementinstrument capable of handling the acquisition, transfer, analysis, anddisplay of large quantities of waveform data as well as complexwaveforms has been described, it should be appreciated that theapparatus and method for a test and measurement instrument hereindescribed are also suitable for use as a logic analyzer, signal sourceinstrument, real-time spectrum analyzer, or any other analyticalinstrument requiring multiple channels for data collection. Furthermore,any other suitable type of memory in addition to dynamic random accessmemory (DRAM) could be utilized.

Therefore, the foregoing is considered as illustrative only of theprinciples of the invention. Further, since numerous modifications andchanges will readily occur to those skilled in the art, it is notdesired to limit the invention to the exact construction and operationshown and described, and accordingly, all suitable modifications andequivalents may be resorted to, falling within the scope of theinvention.

1. A method of processing waveform data from a device under test (DUT)comprising the steps of: providing a test and measurement instrumentcomprising a plurality of processors, a plurality of memory controllers,wherein each processor is connected to its own memory controller,memory, wherein each memory controller is connected to its own memory, aplurality of bridges, wherein each processor is connected to its ownbridge, a plurality of system buses, wherein each bridge is connected toits own system bus, a plurality of acquisition modules having signal businterfaces and acquisition memory, wherein each system bus is connectedto its own acquisition module and has its own acquisition hardware, andwherein each piece of acquisition hardware comprises a direct memoryaccess machine that can transfer data to any portion of the memory, anda plurality of signal sources, wherein each signal source is connectedto its own signal bus interface; attaching the DUT to a signal source tobe measured, wherein at least one channel of the signal source is inelectronic communication with at least one of the acquisition modules;collecting data from the DUT; storing the collected data from the DUT inthe at least one of the acquisition modules; dividing the collected datafrom the DUT into a plurality of pieces; assigning the plurality ofpieces to the plurality of system buses; transferring the plurality ofpieces to the memory connected to the processors by moving the pluralityof pieces in parallel over their assigned system buses; processing theplurality of pieces with the plurality of processors; and displaying theresults obtained by processing the priority of pieces with the pluralityof processors.
 2. The method of processing waveform data from a deviceunder test (DUT) as defined in claim 1, further comprising a pluralityof high-speed interconnects, wherein the high-speed interconnectsconnect the processors to one another.
 3. The method of processingwaveform data from a device under test (DUT) as defined in claim 2,wherein the high-speed interconnects are used as the system buses. 4.The method of processing waveform data from a device under test (DUT) asdefined in claim 1, wherein at least one of the plurality of processorsis a specialized processor selected from the group comprising graphicsprocessing units, digital signal processors, and field-programmable gatearrays.
 5. The method of processing waveform data from a device undertest (DUT as defined in claim 1, wherein each processor is connected toits own memory element.
 6. The method of processing waveform data from adevice under test (DUT) as defined in claim 5, wherein the memoryelements are interconnected.
 7. The method of processing waveform datafrom a device under test (DUT) as defined in claim 5, wherein eachmemory element is interconnected to at least another of the memoryelements by way of the processor to which it is connected.
 8. The methodof processing waveform data from a device under test (DUT) as defined inclaim 1, wherein each processor is a multicore processor.
 9. The methodof processing waveform data from a device under test (DUT) as defined inclaim 1, including a display connected to each of the processors fordisplaying images based on signals acquired by the instrument.
 10. Themethod of processing waveform data from a device under test (DUT) asdefined in claim 1, wherein the display is connected to each of theprocessors by way of the bridges.
 11. A method of processing waveformdata from a device under test (DUT) comprising the steps of: providing atest and measurement instrument comprising a plurality of processors,memory connected to the processors, a plurality of bridges, wherein eachprocessor is connected to its own bridge, a plurality of system buses,wherein each bridge is connected to its own system bus, a plurality ofacquisition modules each having its own signal bus interface, whereineach system bus is connected to its own acquisition module and has itsown acquisition hardware, and wherein each piece of acquisition hardwarecomprises a direct memory access machine that can transfer data to anyportion of the memory, and a plurality of signal sources, wherein eachsignal source is connected to its own signal bus interface; attachingthe DUT to a signal source to be measured, wherein at least one channelof the signal source is in electronic communication with at least one ofthe acquisition modules; collecting data from the DUT; storing thecollected data from the DUT in the at least one of the acquisitionmodules; dividing the collected data from the DUT into a plurality ofpieces; assigning the plurality of pieces to the plurality of systembuses; transferring the plurality of pieces to the memory connected tothe processors by moving the plurality of pieces in parallel over theirassigned system buses; processing the plurality of pieces with theplurality of processors; and displaying the results obtained byprocessing the priority of pieces with the plurality of processors. 12.The method of processing waveform data from a device under test (DUT) asdefined in claim 11, wherein at least one of the plurality of processorsis a specialized processor selected from the group comprising graphicsprocessing units, digital signal processors, and field-programmable gatearrays.
 13. The method of processing waveform data from a device undertest (DUT) as defined in claim 11, wherein each processor is a multicoreprocessor.
 14. The method of processing waveform data from a deviceunder test (DUT) as defined in claim 11, including a display connectedto each of the processors for displaying images based on signalsacquired by the instrument.
 15. The method of processing waveform datafrom a device under test (DUT) as defined in claim 11, wherein thedisplay is connected to each of the processors by way of the bridges.